This invention relates to a cache memory control device and, more particularly, to a cache control system usable with advantage for command pre-fetch in a multi-processor system.
FIG. 11 shows an exemplary structure of a conventional communication LSI and more specifically a structure of a single PHY (physical layer) LSI of ADSL (Asymmetrical Digital Subscriber Line) modem. This ADSL is a high-speed digital transmission system in which the speed from a subscriber accommodating station of a communication undertaker to user""s premises (downstream) is asymmetrical with respect to that from the user""s premises to the accommodating station (upstream) and which uses a pre-existing telephone cable. A signal processor 8 which is adapted for performing digital signal processing on a communication LSI 200C, a baseband unit 9 and an ATM (asynchronous transfer mode) TC (transmission convergence) 10 make up a communication system hardware. The signal processor 8 includes an interfacing circuit 6 made up of a driver receiver circuit of a line (line), a converting circuit 7, made up of a digital-analog converting circuit (D-A) 7-1 for digital-analog converting transmission signals, and an analog-digital converting circuit (A-D) 7-2 for analog-digital converting transmission signals. The communication LSI 200C also includes a processor (CPU) 2, a work RAM 3, an instruction RAM 5 made up of plural RAM banks (eight banks in FIG. 11) in which commands to be executed in the processor 2 are pre-fetched and stored, and an instruction RAM controller 1C. The processor 2 is connected over an internal bus 4 to the communication system hardware, such as work RAM 3, instruction RAM controller 1C and the signal processor 8 etc. The ATM TC (transmission convergence) 10 exchange data with e.g., an upper layer of the PHY (physical layer) supported by the communication LSI 200C.
An external instruction ROM (read-only memory) 12, having an instruction data queue (instructions (commands) and data for executing communication control in the processor 2) stored therein, is externally mounted to the LSI 200C. The instruction RAM controller IC (cache controller) pre-fetches instruction data from the external instruction ROM 12 for storage in a relevant bank in the instruction RAM 5.
The instruction RAM controller IC includes a command register 11C for pre-fetch, as a control register. Even if there is no cache error, the processor 2 writes a pre-fetch request command in the command register 11C at an arbitrary time point to update the instruction RAM 5.
In this command register 11C, start addresses of instruction data, pre-fetched from the instruction RAM 12, and bank numbers of the instruction RAM 5, in which to load the pre-fetched instruction data, are set, and instruction data read out from a relevant address are written in a relevant bank in the instruction RAM 5 in an amount corresponding to the bank memory capacity.
With the instruction RAM 5 being made up of plural banks, the contents of a given bank of a given one of the instruction RAMs 5 can be updated during the accessing of another bank to render queuing of cache updating processing unnecessary to improve the processing performance.
Meanwhile, as to a cache memory system in which the cache memory is made up of plural banks, a cache controller is provided with a command register, and a cache update command is set in the command register under a command from the processor to enable loading (pre-fetch) command to the cache memory at an arbitrary time even if there has occurred no cache error, reference may be had e.g., to the JP Patent Kokai JP-A-11-143775.
Since plural pre-fetch requests are not superposed in this configuration of the signal PHY type LSI 200C, there is provided no function for determining the priority sequence of the pre-fetch requests.
FIG. 12 shows the configuration of a multi-PHY type LSI 200D, in which plural single (sole line) PHY type LSI 200Cs, shown in FIG. 11, are used to allow to cope with plural lines.
Referring to FIG. 12, circuit blocks 1001 to 1004 are provided for each PHY. Each of the circuit blocks 1001 to 1004 includes communication hardware comprised of a CPU 2, an instruction RAM controller 1C, an instruction RAM 5, a signal processor 8 and a baseband processor 9.
Referring to FIG. 12, since no measures are taken to enable the co-owning of the external instruction ROM, four external instructions ROMs 12 are each externally connected to each of PHYs of the LSI 200Ds adapted to cope with four lines. The LSI 200 is in need of a number of terminals corresponding to the number of terminals of these four instructions ROMs. For example, if an address signal is of a 20-bit width and the data is of 8-bit width, 112 terminals are required in order to cope with four instruction ROMs. The number of the terminals is increased further if control signals such as chip enable signals etc. are taken into consideration.
The conventional multi-processor system for coping with plural lines, as described above, has a drawback that a number of external ROM interfaces corresponding to the number of lines (PHYs) to be supported, are required, thus increasing the number of the LSI external terminals by multi-physical layering, termed as xe2x80x9cmulti-PHYingxe2x80x9d herein.
In particular, the program stored in the instruction ROM is increased in size, as the communication control is becoming complex and as control function is diversified, thus increasing the memory capacity of the instruction ROM. In keeping up therewith, the number of address signals of the instruction ROM is increased. Under this situation, the configuration shown in FIG. 12 leads directly to an increased number of LSI pins.
Moreover, since plural external instruction ROMs are required in association with the number of lines, it offers a poor cost reducing effect per line, too.
Also, high-speed processing is required in cache memory control and in pre-fetch control, such that deterioration in the control performance reflects itself readily in the processing performance of the processor. Thus, in case where, in the communication circuit in need of high-speed processing, a configuration is employed such that the instruction ROM is co-owned by the respective PHYs, measures for suppressing the lowering of the processing performance are necessitated.
It is therefore an object of the present invention to provide a cache memory control device in which an external instruction ROM, having stored therein program commands for loading in the cache memory, can be co-owned by plural processors, and in which the lowering of the pro performance of the processor can be suppressed to a minimum.
It is another object of the present invention to provide a cache memory control device in which the number of external terminals of the LSI having plural processors can be reduced. Other objects, features and advantages of the present invention will become apparent from the following description of preferred embodiments and the claims.
According to a first aspect of the present invention, there is provided a novel cache memory control device for a multi-processor system having a plurality of processors. The cache memory control device comprises a plurality of cache memories provided in association with a plurality of the processors, respectively; a memory device co-owned by a plurality of the cache memories having stored therein instruction data to be stored in each of the cache memories; and a plurality of command registers associated with the cache memories for controlling updating of the cache memories in association with respective ones of the plural cache memories. Each of the cache memories stores therein instruction data pre-read from the memory device, and the instruction data is used in the processor corresponding to each of the cache memories. Each of the processors associated with each of the cache memories writing cache memory updating request commands, including information on time allowance until updating of the cache memories, in the command register associated with the cache memories, so that a cache memory updating request is output to a pre-fetch controller. The pre-fetch controller includes means for selecting a cache memory updating request, based on the time allowance information of a plurality of updating requests for the plural cache memories, if such plural updating requests for the cache memories are output. The instruction data is read out from the memory device in accordance with the selected cache memory updating request to update the contents of the so-selected cache memory.
According to a second aspect of the present invention, there is provided a cache memory control device for a multi-processor system having a plurality of processors, comprising: a plurality of cache memories provided in association with a plurality of the processors, respectively; a memory device co-owned by a plurality of the cache memories having stored therein instruction data to be stored in each of the cache memories, and a plurality of command registers associated with the cache memories for controlling updating of the cache memories in association with respective ones of the plural cache memories. Each of the cache memories stores therein instruction data pre-read from the memory device, and the instruction data is used in each of the processors corresponding to each of the cache memories.
Each of the processors associated with each of the cache memories writes a cache memory updating request command, inclusive of a readout start address of the memory device, in the command register associated with each the cache memory, to output a cache memory updating request to a pre-fetch controller. The pre-fetch controller includes means for broadcast-transferring to the plural cache memories a readout start address of the memory device output along with the cache memory updating request and instruction data read out from the memory device. The contents of the cache memory are updated by the broadcast-transferred instruction data if the readout start address broadcast-transferred from the pre-fetch controller coincides with a readout address of the memory device updating an own cache memory. A plurality of the cache memories are enabled to be updated simultaneously responsive to updating requests of plural cache memories the readout addresses of the memory device of which coincide with one another.
In the present invention, the cache memory may be comprised of plural banks and plural command registers may be provided for each of the cache memories.
As will become clear from the following description, the above objects can also be accomplished by the features set forth in the respective claims, the entire disclosure of the appended claims being incorporated herein by reference thereto.
In the following, particular aspects of the present invention are mentioned.
According to a third aspect, a cache memory control device is provided in a multi-processor system adapted for a plurality of channels or lines, and including a processor, a cache memory and a cache memory controller for each channel or line, the cache memory control device comprising:
a sole common memory device common through the cache memories, for storage of instruction data executed by each processor, and
means for exercising control so that, if pre-fetch requests are issued simultaneously from plural cache controllers, pre-fetch of the instruction data from the instruction memory device to the cache memory is performed beginning from a cache memory with the least time allowance, based on the information indicating the time allowance until a scheduled timing of actual use of the instruction data pre-fetched to the cache memory.
According to a fourth aspect, there is also provided a cache memory control device in a multi-processor system adapted for a plurality of channels or lines, and including a processor, a cache memory and a cache memory controller for each channel or line, the cache memory control device comprising:
a sole common memory device common through the cache memories, for storage of instruction data executed by each processor, and
means for broadcasting instruction data pre-fetched from the memory device to a plurality of the cache memory controllers which issued pre-fetch requests when there are a plurality of pre-fetch requests having coincident pre-fetch start addresses of the memory device specified by the pre-fetch requests from the cache controllers.
According to a fifth aspect, there is provided a multi-processor system having a processor, a cache memory and a cache memory controller for each of physical layers of communication control, and adapted for a plurality of channels or lines, wherein
an instruction memory device for storage of instruction data forming a program loaded in a cache memory of each processor of a plurality of the physical layers is co-owned by a plurality of the physical layers;
in a pre-fetch control device for pre-fetching instruction data from the instruction memory device, plural interfaces for controlling the accessing to the instruction memory device are collected into a sole interface;
in issuing a pre-fetch request of instruction data, the cache memory control device of each physical layer also outputting to the pre-fetch control device an information pertinent to the time allowance until the instruction data are needed by the cache memory associated with the cache memory control device;
the pre-fetch control device including means for selecting a pre-fetch request with a smaller one of the time allowance if pre-fetch requests are output simultaneously from the plural cache memory control devices.
According to a sixth aspect, there is provided a communication control device of a multi-processor configuration comprising, for each of a plurality of physical layers of communication control, a communication-based circuit, a processor for controlling the communication-based circuit, an instruction random access memory RAM for pre-fetching and storing instruction data fetched by the processor and an instruction RAM controller for controlling the instruction RAM, the communication control device comprising:
a common one instruction ROM for storing the instruction data for the plural physical layers; and
one pre-fetch controller for the plural physical layers for controlling pre-fetch from the instruction ROM;
the instruction RAM controller of each physical layer outputting an information pertinent to time allowance for a pre-fetch request for the instruction data;
wherein
if a plurality of the pre-fetch requests are issued simultaneously from each of the instruction RAM controllers, the pre-fetch controller selects a pre-fetch request having the least time allowance.
According to a seventh aspect, there is provided a communication control device of a multi-processor configuration comprising, for each of a plurality of physical layers of communication control, a communication-oriented circuit, a processor for controlling the communication-oriented circuit, an instruction random access memory RAM for pre-fetching and storing instruction data fetched by the processor and an instruction RAM controller for controlling the instruction RAM, the communication control device comprising:
a common one instruction ROM for storing the instruction data for the plural physical layers; and
one pre-fetch controller for the plural physical layers for controlling pre-fetch from the instruction ROM;
the instruction RAM controller of each physical layer outputting a pre-fetch start address to a pre-fetch request for the instruction data;
the pre-fetch controller operating, responsive to the pre-fetch request, for broadcast-transferring a pre-fetch start address for the instruction ROM and instruction data pre-fetched by the pre-fetch controller from the instruction ROM to the plural instruction RAM controllers.
According to an eighth aspect, there is provided a semiconductor integrated circuit device of a multi-processor configuration capable of coping with a plurality of lines, and which includes, for each of a plurality of physical layers of communication control, a communication-oriented circuit, a processor for controlling the communication-oriented circuit, an instruction random-access memory RAM operating as a cache memory for the processor and an instruction RAM controller for controlling the instruction RAM, the semiconductor integrated circuit device comprising:
an external instruction storage device for the semiconductor integrated circuit device, in which are stored instruction data to be loaded in each instruction RAM in each of the physical layers;
the instruction RAM being of a plural bank configuration in which, when one bank is being rewritten, the processor is able to access another bank, with the instruction data being rewritten in each bank in an amount corresponding to a volume of the bank read out from the instruction storage device;
the instruction RAM controller of each physical layer having a pre-fetch command register accessed by the processor;
there being set in the command register a start address of the instruction memory device to be pre-fetched, a bank number of the instruction RAM in which the pre-fetched instruction data is loaded and an information pertinent to time allowance, i.e., deadline time until the instruction data is used, subject to a pre-fetch request command from the processor;
the information pertinent to time allowance as set in the command register being output to a pre-fetch controller along with a pre-fetch request signal and the start address;
there being provided a common one of the pre-fetch controller for a plurality of the instruction RAM controllers of the physical layers, the pre-fetch controller being provided with an interfacing unit for the instruction memory device;
the pre-fetch controller including means for selecting a pre-fetch request with the least time allowance when a plurality of pre-fetch requests from the instruction RAM controllers of the physical layers are being output simultaneously;
the instruction data of a specified bank of the instruction RAM being updated responsive to the selected pre-fetch request.
According to a ninth aspect, there is provided a semiconductor integrated circuit device of a multi-processor configuration coping with a plurality of lines, and which includes, for each of a plurality of physical layers, termed PHYs, of communication control, a communication-associated circuit, a processor for controlling the communication-associated circuit, an instruction random-access memory RAM operating as a cache memory for the processor and an instruction RAM controller for controlling the instruction RAM, the semiconductor integrated circuit device comprising:
an external instruction storage device for the semiconductor integrated circuit device, in which are stored instruction data to be loaded in each instruction RAM in each of the PHYs;
the instruction RAM being of a plural bank configuration in which, when one bank is being rewritten, the processor is able to access another bank, with the instruction data being rewritten in each bank in an amount corresponding to a volume of the bank read out from the instruction storage device;
the instruction RAM controller of each PHY having a pre-fetch command register accessed by the processor;
there being set in the command register a start address of the instruction memory device to be pre-fetched, and a bank number of the instruction RAM in which the pre-fetched instruction data is loaded;
there being provided a common one of the pre-fetch controller for a plurality of the instruction RAM controllers of the PHYs, the pre-fetch controller being provided with an interfacing unit for the instruction memory device;
the start address as set in the command register being output to the pre-fetch controller along with a pre-fetch request signal;
the pre-fetch controller including means for broadcasting the start address to instruction RAM controllers of a totality of PHYs, responsive to a pre-fetch request from the instruction RAM controller, the broadcasting means also broadcasting the instruction data read out from the instruction memory device to the instruction RAM controllers of the totality of PHYs;
the instruction RAM controllers of the PHYs including means for comparing whether or not the start address of the broadcast-transferred instruction data coincides with a start address as set in a command register of an own instruction RAM controller, the broadcast-transferred instruction data being written on coincidence of the broadcast-transferred instruction data in a specified bus of the instruction RAM.